Frequently Asked Questions Q: How are the interrupts routed on the Gateway 9315 motherboard?A: The 9315 server motherboard interrupt architecture accommodates both PC-compatible PIC mode and APIC mode interrupts through use of the integrated I/O APICs in the 6300ESB ICH.
Legacy interrupt routing
For PC-Compatible mode, the 6300ESB ICH provides two 82C59-compatible interrupt controllers. The two controllers are cascaded with interrupt levels 8-15 entering on level 2 of the primary interrupt controller (standard PC configuration). A single interrupt signal is presented to the processors, to which only one processor will respond for servicing. The 6300ESB ICH contains configuration registers that define which interrupt source logically maps to I/O APIC INTx pins.
Both PCI and IRQ types of interrupts are handled by the 6300ESB ICH. The 6300ESB ICH translates these to the APCI bus. The numbers in the following table indicate the 6300ESB ICH PCI interrupt input pin to which the associated device interrupt (INTA, INTB, INTC, INTD) is connected. The 6300ESB ICH I/O APIC exists on the I/o APIC bus with the processors.
APIC interrupt routing
For APIC mode, this server motherboard interrupt architecture incorporates two Intel® I/O APIC devices to manage and broadcast interrupts to local APICs in each processor. The Intel I/O APICs monitor each interrupt on each PCI device including PCI slots in addition to the ISA campatibility interrupts IRQ(0-15). When an interrupt occurs, a message corresponding to the interrupt is sent across a three-wire serial interface to the local APICs. The APIC bus minimizes interrupt latency time of compatibility interrupt sources. The I/O APICs can also supply greater than 16 interrupt levels to the processor(s). This APIC bus consists of an APIC clock and two bidirectional data lines.
Legacy interrupt sources
The following table recommends the logical interrupt mapping of interrupt sources on the server motherboard. The actual interrupt map is defined using configuration registers in the 6300ESB ICH.
Serialized IRQ support
This server motherboard supports a serialized interrupt delivery mechanism. Serialized Interrupt Requests (SERIRQ) consists of a start frame, a minimum of 17 IRQ / data channels, and a stop frame. Any slave device in quiet mode may initiate the start frame. While in continuous mode, the start frame is initiated by the host controller.