Features
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  • JEDEC-standard 184-pin dual in-line memory module (DIMM)
  • Fast data transfer rate: PC3200
  • CAS Latency 3
  • Utilizes 400 MT/s DDR SDRAM components
  • Supports ECC error detection and correction
  • 256MB (32 Meg × 72)
  • VDD= VDDQ= +2.6V
  • VDDSPD = +2.3V to +3.6V
  • +2.6V I/O (SSTL_2 compatible)
  • Commands entered on each positive CK edge
  • DQS edge-aligned with data for READs; centeraligned with data for WRITEs
  • Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle
  • Bidirectional data strobe (DQS) transmitted/ received with data-i.e., source-synchronous data capture
  • Differential clock inputs (CK and CK#)
  • Four internal device banks for concurrent operation
  • Programmable burst lengths: 2, 4, or 8
  • Auto precharge option
  • Auto Refresh and Self Refresh Modes
  • 7.8125µs maximum average periodic refresh interval
  • Serial Presence-Detect (SPD) with EEPROM
  • Programmable READ CAS latency
  • Gold edge contacts