The graphic is an example of a DDR SDRAM module.
The DDR SDRAM modules use a double data rate (DDR) architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM module effectively consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
Read and write accesses to the DDR SDRAM modules are burst oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.
The DDR SDRAM modules provide for programmable READ or WRITE burst lengths of two, four, or eight locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access.
As with standard SDR SDRAM modules, the pipelined, multibank architecture of DDR SDRAM modules allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time.