82443BX PAC Chip
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The Intel 440BX PCI set includes a Host-PCI bridge integrated with both an optimized Dynamic Random Access Memory (DRAM) controller and an Accelerated Graphics Port (AGP) interface. The input/output (I/O) subsystem of the 440BX is based on the PIIX4E, which is a highly integrated PCI-ISA/IDE Accelerator Bridge. This chip set consists of the Intel 82443BX PCI/AGP controller (PAC) and the Intel 82371EB PCI/ISA IDE Xccelerator (PIIX4E) Bridge chip.

82443BX PAC chipThe 82443BX PCI/AGP controller (PAC) chip provides bus-control signals, address paths, and data paths for transfers between the processor's host bus, PCI bus, the Accelerated Graphics Port (AGP), and main memory. The PAC features:
  • Processor Interface Control
    • Support for Processor host bus speeds of 66 to 100 megahertz (MHz)
    • 32-bit addressing
    • Desktop Optimized GTL+ compliant host bus interface
  • Integrated DRAM Controller
    • Up to three double sided DIMMs
    • Supports synchronous 66- or 100-MHz static RAM (SRAM)
    • 16- and 64-Mbit devices with 2 kilobytes (KB), 4 KB and 8 KB page sizes
    • DIMM serial presence detect via SMBus interface
    • x4, x8, x16 and x32 DRAM widths
    • Symmetrical and asymmetrical DRAM addressing
    • Supports +3.3V only DIMM DRAM configurations
  • Accelerated Graphics Port Interface
    • Complies with AGP specification
    • Supports +3.3V AGP devices with data transfer rates up to 133 MHz
    • Synchronous coupling to the host-bus frequency
  • PCI Bus Interface
    • Complies with PCI specification revision 2.1, +5V 33MHz interface
    • Asynchronous coupling to the host-bus frequency
    • Data streaming support from PCI to DRAM
    • Supports five PCI bus masters in addition to the host and PCI to ISA input/output (I/O) bridge
    • Support for concurrent host, AGP, and PCI transactions to main memory
    • PCI parity generation support
  • Data Buffering
    • DRAM write buffer with read-around-write capability
    • Dedicated host to DRAM, PCI0 to DRAM, and PCI1/AGP to DRAM read buffers
    • AGP dedicated inbound/outbound first in/ first outs (FIFOs) 133/66Mhz, used for temporary data storage
  • Power management functions
  • SMBus support for desktop management functions
  • Supports System Management Mode (SMM)