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L - Intel 82801BA ICH2 Show Part Numbers Hide Part Numbers 2511440, 2511441, 2511445, 2512455, 2512456, 2512460, 2512814, 2512818, 2513264, 2513268,
2513269, 2513274, 2513278, 2513279, 2513285, 2513289, 2513290, 2513374, 2513388, 2513390,
2513393, 2513394, 2513399, 2513401, 2513404, 2513405, 2513410, 2513412, 2513418, 2513421,
2513431, 2513432, 2513436, 2513440, 2513441, 2513442, 2513444, 2513445, 2513708, 2513711,
2513714, 2513715, 2513720, 2513722, 2513725, 2513726, 2513869, 2513872, 2513873, 2513874,
2513920, 2513921, 2513926, 2513976, 2514096, 2514097, 2514098, 2514674, 2514675, 2514676,
2514677, 2514678, 2514679, 2514722, 2514724, 2514726, 2514728, 2514730, 2514731, 2514738,
2514777, 2514977
 | The Intel ICH2 Logic controller is responsible for the following:
- Integrated Intel Kinnereth 10/100 LAN controller
- PCI Bus Master interface
- CSMA/CD Protocol Engine
- Serial CSMA/CD unit interface that supports the 82562ET (10/100 megabits per second (Mbps) Ethernet) physical layer interface device
- PCI Power Management
- Supports APM
- Supports ACPI technology
- Supports Wake up from suspended state (Wake-On-LAN technology)
- PCI bus interface
- Supports PCI bus at 33 megahertz (MHz)
- Supports PCI Specification Revision 2.2
- Supports up to six master devices on PCI bus
- Integrated IDE controller
- Supports Ultra DMA 33/66/100
- Supports PIO Mode 4 transfers
- Separate IDE connections for primary and secondary controllers
- Independent timing of up to four drives
- Two separate USB controllers supporting two USB ports
- UHCI implementation with four ports
- Supports wake from sleep states S1,S3, and S4
- Supports legacy keyboard and mouse software
- AC '97 link for audio and modem codecs
- AC '97 2.1 compliant
- Separate independent PCI functions for audio and modem
- Supports wake-up events
- Power Management
- Support for APM-based legacy power management
- ACPI 1.0b compliant
- Low pin count (LPC) bus
- Allows connection of legacy ISA and X-bus devices
- Supports two master DMA devices
- Real-time clock
- 256-byte battery backed CMOS RAM
- Hardware implementation to indicate century rollover
- SM bus host interface allows CPU to communicate with clock
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