N - Intel Logic Controller       Show Part Numbers       Hide Part Numbers 2511081, 2511083, 2511092, 2511095, 2511096, 2511371, 2511372, 2511373, 2511374, 2511375, 2511378, 2511379, 2511380, 2511546, 2511559, 2511608, 2511639, 2511654, 2511655, 2511656, 2511658, 2511659, 2511660, 2511702, 2511742, 2512266, 2512267, 2512353, 2512354, 2512463, 2512471, 2512472, 2512473, 2512474, 2512475, 2512476, 2512478, 2512479, 2512480, 2512481, 2512483, 2512489, 2512847, 2512848, 2512871, 2512872, 2513114, 2513120, 2513193, 2513464, 2513465, 2513499, 2513500, 2513540, 2513637, 2513638, 2513969, 2514024, 2514052, 2514150, 2514151, 2514152, 2514153, 2514154, 2514155, 2514156, 2514157, 2514158, 2514159, 2514160, 2514161, 2514210, 2514211, 2514212, 2514287, 2514288, 2514289, 2514290, 2514291, 2514292, 2514437, 2514438, 2514439, 2514494, 2514910, 2514911, 2514912, 2514913, 2515101, 2515103, 2515104, 2515110, 2515112, 2515113, 2515114, 2516124, 2516129, 2516130, 2516131, 2516133, 2516134, 2516135, 2516137, 2516138, 2516139, 2516140, 2516141, 2516142, 2516143, 2516144, 2516145, 2516146, 2516147, 2516148, 2516149, 2516150, 2516151, 2516152, 2516153, 2516154, 2516155, 2516156, 2516170, 2516171, 2516172, 2516173, 2516174, 2516175, 2516176, 2516177, 2516178, 2516179, 2516180, 2516181, 2516182, 2516183, 2516184, 2516185 The Intel ICH Logic controller is responsible for the following: PCI Bus interface Supports PCI bus at 33-megahertz (MHz) Supports PCI Specification Rev 2.2 Supports up to six Master Devices on PCI bus Integrated IDE Controller Supports Ultra DMA 33/66 Supports PIO Mode 4 Transfers Separate IDE Connections for Primary and Secondary controllers Independent timing of up to four drives Universal Serial Bus UHCI Implementation with four ports Supports Wake from sleep states S1, S3, and S4. Supports legacy Keyboard/Mouse software AC'97 Link for Audio and Modem CODECs AC'97 2.1 Compliant Separate independent PCI functions for Audio and Modem Supports wake-up events Power Management Support for APM-Based legacy power management ACPI 1.0b Compliant Low Pin Count (LPC) bus Allows connection of legacy ISA and X-Bus devices Supports two master DMA devices Real-Time clock 256-byte battery backed CMOS RAM Hardware implementation to indicate century rollover SM Bus Host interface allows CPU to communicate with clock