| Feature |
Specification |
| General |
| Density |
512 MB |
| Organization |
64 M × 72 |
| Performance Range |
Speed @ CL3 - 400 Mbps
Speed @ CL4 - 533 Mbps
Speed @ CL5 - 667 Mbps
|
| JEDEC standard |
1.8 V ± 0.1 V Power Supply |
| DIMM Size |
64 M × 72, maximum height 30.00 millimeters (mm) |
| DDR2 SDRAM Package |
60 ball FBGA - 128 M × 4 / 64 M × 8 |
| Banks |
4 |
| Chips |
9 - 64 M × 8 |
| CAS |
Posted |
| CAS Latency |
- Programmable CAS Latency: 3, 4, 5
- Programmable Additive Latency: 0, 1 , 2 , 3 and 4
- Write Latency(WL) = Read Latency(RL) -1
|
| Burst Length |
4, 8 (Interleave / nibble sequential) |
| Burst Mode |
Programmable Sequential / Interleave Burst Mode |
| Data Strobe |
Bi-directional Differential |
| Impedance Adjustment |
Off-Chip Driver(OCD) |
| Termination |
On Die Termination with selectable values(50/75/150 ohms or disable) |
| Parity Register |
Yes |
| Refresh type |
PASR(Partial Array Self Refresh) |
| Refresh time |
Average refresh period 7.8 µs at lower than a TCASE 85° C 3.9 µs at 85° C < TCASE < 95° C
Support high temperature self-refresh rate enable feature |
| Refresh to Active / Refresh Command Time |
105 ns |
| Operating Temperature |
0 to 90° C |
| RoHS Compliant |
Yes |