| DRAM supply voltage |
Minimum: 3.0 V and Maximum: 3.6 V |
| DIMM size |
Length: 133.35 mm
Maximum module thickness: 4.00 mm
PCB thickness: 1.27 mm
Maximum height: 31.75 mm
Lead pitch: 1.02 mm |
| Data bits |
72 |
| Pin quantity |
JEDEC and industry standard pinout, 168-pin DIMM |
| Pin type |
LVTTL compatible, Gold Contacts 0.75 (minimum) over NI plating 2 micrometers |
| DRAM type |
32 @ 8 Mb × 72 |
| CAS latency |
CL = 2 or 3 @ Tac (maximum) = 6.0 ns (rated at 50 pf all outputs switching or 5.2 ns @ 0 pf)
Trp (minimum) = 2 clks, Trcd (minimum) = 2 clks, Trc (minimum) = 7 clks
|
| Parity |
Yes |
| ECC |
Yes |
| Refresh type |
AUTO (CBR) |
| Refresh time |
4,096 refresh cycles per 64 ms |
| DIMM design |
Per Intel PC SDRAM Unbuffered DIMM Specification v1.0 |
| Discretes |
Per Intel PC SDRAM Specification v1.51 |
| Clocks |
4 clocks per DIMM with proper termination of unused clocks |
| PCB layout |
6-layer using glass epoxy material Must have both a full ground plane layer and power plane layer. PCB must be designed to meet trace velocity/impedance parameters. All signals must meet their routing topology and trace length requirements. |
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