| DRAM Supply Voltage |
Min: 3.0v and Max: 3.6v |
| DIMM size |
16M x 72, 128MB, Maximum height 38.25mm |
| Data bits |
72 |
| Pin quantity |
JEDEC & Industry Standard Pinout, 168 Pin DIMM |
| Pin type |
LVTTL Compatible, Gold Contacts 0.75 (min) over NI plating 2 micrometers |
| DRAM type |
8MB x 8, Qty 18, using 54-pin TSOP(II) (400 mil) packaging (2 ext. ROWS) |
| CAS Latency |
CL=2 or 3@ Tac (max) = 6.0ns (rated at 50pf all outputs switching or 5.2ns @ 0pf)
Trp (min) = 2clks, Trcd (min) = 2clks, Trc (min) = 7clks
|
| Parity |
ECC |
| Refresh type |
AUTO (CBR) |
| Refresh time |
4K cycle refresh distributed across 64ms 15.6usec per row |
| Addressing |
Asymmetrical 12 rows, 9 columns, 4 internal banks |
| DIMM Design |
Per Intel PC SDRAM Unbuffered DIMM Specification v1.0 |
| Discretes |
Per Intel PC SDRAM Specification v1.51 |
| Clocks |
4 Clocks per DIMM w/ proper termination of unused clocks |
| PCB Layout |
6 layer using glass epoxy material Must have both a full ground plane layer and power plane layer PCB must be designed to meet trace velocity/impedance parameters All signals must meet their routing topology and trace length requirements |
United States
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