| Feature |
Specifications |
| DRAM supply voltage: |
Minimum: 3.0 volts (v) and Maximum: 3.6v |
| DIMM size: |
16M × 64, 128 megabyte (MB), maximum height 38.25 millimeter (mm) |
| Data bits: |
64 |
| Pin quantity: |
JEDEC & industry standard pinout, 168 pin DIMM |
| Pin type: |
LVTTL compatible, Gold contacts |
| DRAM type: |
8 megabyte (MB) × 8, quantitiy 16, using 54-pin TSOP(II) (400 mil) packaging (2 ext. BANK) |
| CAS latency: |
CL=2 @ Tac(max) – 6.0ns (rated at 50pf all outputs switching)
Trp(min) = 2clks, Trcd(min) = 2clks, Trc(min) = 7clks |
| Parity: |
No |
| Refresh type: |
AUTO (CBR) |
| Refresh time: |
4 kilobyte (K) cycle refresh distributed across 64 milliseconds (ms)
15.6usec per row |
| Addressing: |
Asymmetrical
12 rows, 8 columns, 4 internal banks |
| DIMM design: |
Per Intel 4-Clk 100 megahertz (MHZ) 64-Bit unbuffered SDRAM DIMM specification |
| Discretes: |
Per Intel PC/100 SDRAM discrete specification, v1.4 |
| Clocks |
4 clocks per DIMM with proper termination of unused clocks |
| PCB layout |
* 6 layer using glass epoxy material. Must have both a full ground plane layer and power plane layer.
* Clock signal routing follows Intel’s specification and does not exceed maximum trace length requirements.
* Data signal routing does not exceed Intel’s maximum trace length requirements. |
United States
(change country or region)