Timing Parameters
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Parameter Symbol CL = 2 CL = 3 Units
    Minimum Maximum Minimum Maximum  
Clock period Tclk 15   15   ns
Clock high time Tch 5   5   ns
Clock low time Tcl 5   5   ns
Input setup times Tsi         ns
DQM#/CS#   3   3   ns
Other   3   3   ns
Input hold times Thi         ns
DQM#/CS#   1.5   1.5   ns
Other   1.5   1.5   ns
Output valid from clock Tac         ns
Restricted configuration     10.0     ns
General configuration     9.0   9.0 ns
Output hold from clock Toh 3   3   ns
CAS to CAS delay Tccd 1   1   Tclk
CAS Bank Delay Tcbd 1   1   Tclk
CKE to clock disable Tcke 1 1 1 1 Tclk
RAS precharge time Trp 3   3   Tclk
RAS Active Time Tras 4   5   Tclk
Activate to command delay (RAS to CAS Delay) Trcd 2   2   Tclk
RAS to RAS bank activate delay Trrd 2   2   Tclk
RAS cycle time Trc 7   8   Tclk
DQM to input data delay Tdqd 0 0 0 0 Tclk
Write Cmd. to input data delay Tdwd 0 0 0 0 Tclk
Mode register set to active delay Tmrd 3   3   Tclk
Precharge to O/P in High-Z Troh 2   3   Tclk
DQM to data in HiZ for read Tdqz 2 2 3 3 Tclk
Data in to precharge Tdpl 2   2   Tclk
Data in to activate/refresh Tdal 5   5   Tclk
DQM to Data mask for write Tdqm 0 0 0 0 Tclk
Power down mode entry Tsb   1   1 Tclk
Self Refresh exit time Tsrx 10   10   ns
Power down exit set up time Tpde 11   11   ns

Note: DIMMs which are intended for 66 megahertz (Mhz) CAS Latency 2 must also support 66 Mhz CAS Latency 3